Design of Low-Leakage SRAM Cells for Sub-10nm Technologies

In the era of aggressively scaled CMOS technologies, static random-access memory (SRAM) plays a critical role in determining the overall power and performance of modern integrated circuits. This paper presents a comprehensive design methodology for low-leakage SRAM cells targeted at sub-10nm technology nodes. We propose modifications to conventional 6T SRAM architecture and evaluate alternative topologies such as 8T and 10T cells for leakage reduction. Simulation results using predictive technology models (PTM) for 7nm FinFET demonstrate significant improvements in leakage current, noise margins, and cell stability under process, voltage, and temperature (PVT) variations. Additional analysis includes layout design considerations, temperature-dependent behavior, and scalability insights for advanced technology nodes.